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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19104

Title: Peak-power Reduction for Multiple-scan Circuits During Test Application
Authors: Lee, Kuen-Jong;Huang, Tsung-Chu;Chen, Jih-Jeen
Contributors: 電子工程學系
Date: 2000
Issue Date: 2014-10-27T08:08:05Z
Abstract: This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.
Relation: Proceedings of the 9th Asian Test Symposium (ATS 2000), : 453-458
Appears in Collections:[電子工程學系] 會議論文

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