English  |  正體中文  |  简体中文  |  Items with full text/Total items : 6469/11641
Visitors : 19807687      Online Users : 229
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search
LoginUploadHelpAboutAdminister

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19121

Title: Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement
Authors: Yang, Cheng-Han;Chou, Yi-Hsian;Huang, Tsung-Chu
Contributors: 電子工程學系
Date: 2008-08
Issue Date: 2014-10-27T08:08:30Z
Publisher: 國立交通大學
Relation: The 19th VLSI Design/CAD Symposium, : 280-283
Appears in Collections:[電子工程學系] 會議論文

Files in This Item:

There are no files associated with this item.



All items in NCUEIR are protected by copyright, with all rights reserved.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback