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NCUEIR > College of Engineering > Department and Graduate Institute of Computer Science and Information Engineering > Proceedings > Item 987654321/10126

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/10126

Title:	The Implementation and Analysis of an All-digital Phase-locked Loop
Authors:	Chen, Po-Yueh;Su, Hung-Lung
Contributors:	資訊工程學系
Keywords:	All-digital phase-locked loop (ADPLL);Digitally Controlled oscillator (DCO);Phase and frequency detector (PFD)
Date:	2006-05
Issue Date:	2012-05-03T09:14:52Z
Publisher:	國立高雄海洋科技大學
Abstract:	An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in eep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity phase and frequency detector (PFD). Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.
Relation:	第四屆微電子技術發展與應用研討會, 國立高雄海洋科技大學, 2009年5月19日
Appears in Collections:	[Department and Graduate Institute of Computer Science and Information Engineering] Proceedings

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