National Changhua University of Education Institutional Repository : Item 987654321/10126
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 6507/11669
造访人次 : 30083235      在线人数 : 802
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 进阶搜寻

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/10126

题名: The Implementation and Analysis of an All-digital Phase-locked Loop
作者: Chen, Po-Yueh;Su, Hung-Lung
贡献者: 資訊工程學系
关键词: All-digital phase-locked loop (ADPLL);Digitally Controlled oscillator (DCO);Phase and frequency detector (PFD)
日期: 2006-05
上传时间: 2012-05-03T09:14:52Z
出版者: 國立高雄海洋科技大學
摘要: An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in eep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity phase and frequency detector (PFD). Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.
關聯: 第四屆微電子技術發展與應用研討會, 國立高雄海洋科技大學, 2009年5月19日
显示于类别:[資訊工程學系] 會議論文

文件中的档案:

档案 大小格式浏览次数
2050401016003.pdf46KbAdobe PDF663检视/开启


在NCUEIR中所有的数据项都受到原著作权保护.

 

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈