National Changhua University of Education Institutional Repository : Item 987654321/11657
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 6487/11649
造访人次 : 28508180      在线人数 : 396
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 进阶搜寻


题名: Combining the Folding and Testing for Programmable Logic Arrays
作者: Wei, Kai-Cheng;Liu, B. D.
贡献者: 資訊工程系
日期: 1994
上传时间: 2012-06-18T02:34:00Z
出版者: World Scientific Publishing
摘要: Different from the previous techniques which treated the folding and testing for PLAs as separate problems, this paper presents a new approach to combine the bipartite folding and testing for PLA’s in the same procedure. Fewer silicon area than other existing comparable techniques is required to make the PLA testable. Experimental results show that this technique can reduce chip area, test length, test storage and time complexity.
關聯: Journal of Circuits systems and Computers, 4(3): 305-317
显示于类别:[資訊工程學系] 期刊論文


档案 大小格式浏览次数
2050400610001.pdf69KbAdobe PDF460检视/开启



DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈