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|Title: ||A Low-Power Direct Digital Frequency Synthesiser|
|Authors: ||Yi, S.-C.;Chen, J.-J.;Lin, C.-H.;Lee, K.-T.|
|Keywords: ||Direct Digital Frequency Synthesiser (DDFS)|
Lookup Table ROM
Digital Circuit Design
|Issue Date: ||2010-11-12T07:20:28Z
|Abstract: ||We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 μm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ROM or multipliers are used, but an external DAC is required if an analog output is desired. Power consumption is 10 mW for a 100 MHz clock, which is significantly less than figures reported previously. System complexity is greatly reduced by using an efficient linear interpolation scheme to approximate a sinusoid function. This has resulted in silicon area utilization of 0.011
mm2. The design would be suitable as an IP core in a low power digital RF transceiver ASIC.
|Relation: ||International Journal of Electronics, 95(6), 2008:593-599(DOI: 10.1080/00207210802155776
|Appears in Collections:||[積體電路設計研究所] 期刊論文|
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