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http://ir.ncue.edu.tw/ir/handle/987654321/19082
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| 題名: | Token Scan Cell for Low Power Testing |
| 作者: | Huang, Tsung-Chu;Lee, Kuen-Jong |
| 貢獻者: | 電子工程學系 |
| 日期: | 2001-05
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| 上傳時間: | 2014-10-27T08:06:18Z
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| 出版者: | Institution of Engineering and Technology |
| 摘要: | A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved. |
| 關聯: | Electronics Letters, 37(11): 678-679 |
| 顯示於類別: | [電子工程學系] 期刊論文
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