English  |  正體中文  |  简体中文  |  Items with full text/Total items : 6469/11641
Visitors : 18463848      Online Users : 246
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search
LoginUploadHelpAboutAdminister

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19082

Title: Token Scan Cell for Low Power Testing
Authors: Huang, Tsung-Chu;Lee, Kuen-Jong
Contributors: 電子工程學系 
Date: 2001-05
Issue Date: 2014-10-27T08:06:18Z
Publisher: Institution of Engineering and Technology
Abstract: A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.
Relation: Electronics Letters, 37(11): 678-679
Appears in Collections:[電子工程學系] 期刊論文

Files in This Item:

File SizeFormat
index.html0KbHTML309View/Open


All items in NCUEIR are protected by copyright, with all rights reserved.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback