Items for Author "Wu, Tsung-Yi" 

Showing 11 items.

Collection	Date	Title	Authors
[電子工程學系] 會議論文	2011-04	A High Speed Design Using Divide-and-Conquer Architecture for Motion Estimation	Wu, Tsung-Yi; Huang, Shi-Yi
[電子工程學系] 期刊論文	2010-12	Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs	Wu, Tsung-Yi; Kao, Tzi-Wei; Lin, How-Rern
[電子工程學系] 會議論文	2010-08	Peak Current Reduction Using an MTCMOS Technique	Lu, Liang-Ying; Wu, Tsung-Yi; Chiou, Lih-Yih; Shi, Jing-Wen
[電子工程學系] 會議論文	2010-01	Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs	Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern
[電子工程學系] 會議論文	2009-05	A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm	Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern
[電子工程學系] 會議論文	2009-05	A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers	Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern
[電子工程學系] 期刊論文	2009	A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates	Lin, How-Rern; Chiu, Wei-Hao; Wu, Tsung-Yi
[電子工程學系] 期刊論文	2009	Low-Leakage and Low-Power Implementation of High-Speed Logic Gates	Wu, Tsung-Yi; Lu, Liang-Ying
[電子工程學系] 會議論文	2008-12	Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates	Wu, Tsung-Yi; Lu, Liang-Ying; Liang, Cheng-Hsun
[電子工程學系] 會議論文	2008-03	IR Drop Reduction Via a Flip-Flop Resynthesis Technique	Wu, Jiun-Kuan; Wu, Tsung-Yi; Lu, Liang-Ying; Chen, Kuang-Yao
[電子工程學系] 會議論文	2007-01	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost	Wu, Tsung-Yi; Tzeng, Jr-Luen; Chen, Kuang-Yao